Modern power semiconductor modules comprise not only power electronic semiconductor components (in particular power semiconductor switches), but also integrated circuits (ICs) as important components. The latter are used e.g. for switching power semiconductor switches or for measuring currents or temperatures. In this context, the term “intelligent power semiconductor modules” (“intelligent power module”, for short: IPM) is often employed. Such IPMs typically comprise, in addition to the power electronics, the required driver circuits (gate drivers) and the like. The operating voltages customary in power semiconductor modules can be in the range of from hundreds of volts to a few kilovolts. These high voltages are present directly at some external contacts (high-voltage contacts) of the ICs (e.g. of the gate drivers), for which reason these IC units require effective insulation. Depending on the application and standards associated therewith, it is thus necessary to maintain spacings between the high-voltage contacts of the ICs and current-carrying parts at low potential (so-called air clearances and creepage paths), such that sufficient insulation is ensured. Insulating a plurality of IC units supplied with high voltage from one another likewise requires specific spacings relative to one another. If a plurality of such ICs are arranged on a printed circuit board (printed circuit card), these lateral spacings of the units on the printed circuit board provide for a large area requirement. The endeavor to obtain ever more compact modules demands a reduction of the area of the printed circuit board.
One possibility for ensuring the required area of the printed circuit board with the insulation remaining the same (i.e. with the creepage path remaining the same) consists in replacing the conventional SMD (SMD=surface mounted device) IC packages by packages having a smaller pitch (pitch=spacing of connection legs) or a BGA (BGA=ball grid array).
However, this method requires an additional insulation layer with which these chip packages have to be coated, which results in an additional work step. Moreover, the production of an insulation layer below the ICs can be realized only with high outlay. The area gained by these methods on the printed circuit board in comparison with the initial situation is only minimal and is therefore at odds with the significantly greater outlay of the insulation requirements (additional insulation layer).